In digital circuits, the clock signal synchronizes communication between different parts within the circuit and between different circuits. Circuits designed to operate with the clock signal may respond at the rising or falling edge of the clock signal. Single data-rate (SDR) memory interfaces normally utilize only either the rising or falling edge to transfer data. Double data-rate (DDR) memory interfaces, on the other hand, transfer data on both the rising edge and falling edge of the clock signal. Thus, the data transfer rate in a DDR memory interface is twice as fast as the transfer rate of a regular SDR memory interface.
As data rates increase, duty cycle distortions may be problematic as the size of the window, during which valid data may be captured, may be reduced and potentially lead to the loss of data. A duty cycle is the fraction of time that the clock or system is in an “active” state. A substantially symmetrical duty cycle is required for most high speed applications as asymmetric duty cycles will make the synchronization of all the clocks in a system more difficult. A symmetrical duty cycle or a 50% duty cycle means each clock period has equal high and low periods. In other words, a clock signal with 50% duty cycle spends half the clock period at logic 1 and the other half at logic 0.
Various duty correction techniques are usually employed to correct duty cycle distortions. Static delay chains that can delay rising and falling edges of the clock signal are generally used. However, as duty cycle distortions normally vary from device to device, it is difficult to use one static delay setting to correct duty cycle distortions in different devices. It is also difficult to find the correct settings for devices operating under different process, voltage and temperature (PVT) conditions as duty cycle distortions also vary under different PVT conditions.
Therefore, it is desirable to have a duty cycle correction circuit that can automatically correct duty cycle distortions in different devices operating under different PVT conditions. It is within this context that the invention arises.